[Abstract]

An interface trap negatively affects the performance of a thin-film transistor (TFT). In the current study, we demonstrate hysteresis-free solution-processed MoS2 TFTs with a significantly reduced trap density of 3.7 × 1010 cm⁻² using a poly(methylmethacrylate) (PMMA) dielectric in a top-gate top-contact (TGTC) device structure, which is much lower than that with a SiO₂ back-gate dielectric layer (7.9 × 1011 cm⁻² ). The TFTs show a field-effect mobility of 7 cm² /V s for both forward and reverse scans, with an ON/OFF current ratio of >106 . In addition, after 3000 s of the bias-stress test, the drain current of the device degrades by only 7%.